Introduction

This exploration will help understand that a processor basically fetches an instruction and then executes it, i.e., fetch and execute cycles, and this process is repeated. The fetch and execute cycle are also referred to as the Instruction Cycle. This is fundamentally how all processors operate no matter how complicated the processor is. Moreover, each of the fetch/execute cycle requires multiple micro-operations, which consists of one or more data transfer operations. Again, since the computer organization design space is vast and depends on the ISA as well as the hardware implementation, we will focus on implementing the fetch and execute cycles for the instructions in the pseudo-ISA (see Module 2) on the pseudo-CPU.

Readings

Module 3: Computer Organization Fundamentals slides - Section 3.3 Fetch & Execute Cycle
Textbook: Section 3.6 Instruction Cycle

Lecture

Fetch and Execute Cycles for Pseudo-CPU (20:36)

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Exercise

For the pseudo-CPU shown in Figure 3.9 in the textbook, explain whether each of the following microoperations can be performed in a single clock cycle. Assume PC and MAR each contain 12 bits, AC and MDR each contain 16 bits, and IR is 4 bits.

MAR ← AC, MDR ← MAR
IR ← MDR, MAR ← MDR
MAR ← MDR, MDR ← M(MAR)
MDR ← AC + 1
AC ← MDR, PC ← PC + 1
PC ← PC + AC

See the solution to the exercise

These two data transfer operations cannot be performed at the same time. This is because both data transfer operations require the Internal Data Bus at the same time.
These two data transfer operations can be performed at the same time. However, the bits that are transferred need to be more specifically defined. That is, MDR is 16 bits, but IR is only 4 bits and MAR is only 12 bits. Thus, the correct way of specifying these two data transfer operations is
- IR ← MDR(15...12), MAR ← MDR(11...0) or
- IR ← MDR(opcode), MAR ← MDR(address)
These two data transfer operations can be performed at the same time. Suppose MDR contain x and MAR contain y. During the clock cycle, M(y) will be performed and the value read will be available at the input of MDR but not yet latched. At the same time, x from MDR will be available at the input of MAR but not yet latched. At the end of the clock, MDR will have M(y) and MAR will have x.  
This data transfer or microoperation cannot be performed. The reason is shown in Figure 3.10 in the textbook. As can be seen, the left input (A) to the ALU is AC and the right input (B) to the ALU can be any one of the registers connected to the Internal Data Bus. However, the result of the ALU operation can only be latched onto the AC.  
These two data transfer operations can be performed at the same time because the PC increment is done independent of the Internal Data Bus.
This data transfer operation or microoperation cannot be performed. The reason is that the increment unit (+1) only accepts PC as input.